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HD64F7047 Datasheet(PDF) 159 Page - Renesas Technology Corp

Part # HD64F7047
Description  Renesas 32-Bit RISC Microcomputer SuperHTMRISC engine Family/SH7000 Series
PDF  764 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

HD64F7047 Datasheet(HTML) 159 Page - Renesas Technology Corp

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Rev. 2.00, 09/04, page 119 of 720
Memory space
Normal mode
DTMR
DTCRA
DTSAR
DTDAR
Memory space
Repeat mode
DTMR
DTCRA
DTSAR
DTDAR
Memory space
Block transfer mode
Register
information
DTMR
DTCRA
DTCRB
DTIAR
DTSAR
DTDAR
Register
information
start address
Figure 8.3 DTC Register Information Allocation in Memory Space
Figure 8.4 shows the correspondence between DTC vector addresses and register information
allocation. For each DTC activating source there are 2 bytes in the DTC vector table, which
contain the register information start address.
Table 8.1 shows the correspondence between activating sources and vector addresses. When
activating with software, the vector address is calculated as H'0400 + DTVEC[7:0].
Through DTC activation, a register information start address is read from the vector table, then
register information placed in memory space is read from that register information start address.
Always designate register information start addresses in multiples of four.
DTBR
DTC vector table
DTC vector address
Transfer information
start address
(upper 16 bits)
Register
information
Memory space
Register information
start address
(lower 16 bits)
Figure 8.4 Correspondence between DTC Vector Address and Transfer Information



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