HD64F7047 datasheet(158/764 Pages) RENESAS

158 / 764 page

Rev. 2.00, 09/04, page 118 of 720

8.3

Operation

8.3.1

Activation Sources

The DTC operates when activated by an interrupt or by a write to DTCSR by software. An

interrupt request can be directed to the CPU or DTC, as designated by the corresponding DTER

bit. At the end of a data transfer (or the last consecutive transfer in the case of chain transfer), the

activation source interrupt flag or corresponding DTER bit is cleared. The activation source flag,

in the case of RXI_2, for example, is the RDRF flag of SCI2.

When a DTC is activated by an interrupt, existing CPU mask level and interrupt controller

priorities have no effect. If there is more than one activation source at the same time, the DTC

operates in accordance with the default priorities.

Figure 8.2 shows a block diagram of activation source control. For details see section 6, Interrupt

Controller (INTC).

IRQ

on-chip

peripheral

Interrupt requests

CPU interrupt requests

(those not designated as

DTC activating sources)

Source flag clear

DTER

INTC

DTC

DTC control

Clear

DTC activation

request

Figure 8.2 Activating Source Control Block Diagram

8.3.2

Location of Register Information and DTC Vector Table

Figure 8.3 shows the allocation of register information in memory space. The register information

start addresses are designated by DTBR for the upper 16 bits, and the DTC vector table for the

lower 16 bits.

The allocation in order from the register information start address in normal mode is DTMR,

DTCRA, 4 bytes empty (no effect on DTC operation), DTSAR, then DTDAR. In repeat mode it is

DTMR, DTCRA, DTIAR, DTSAR, and DTDAR. In block transfer mode, it is DTMR, DTCRA, 2

bytes empty (no effect on DTC operation), DTCRB, DTSAR, then DTDAR.

Fundamentally, certain RAM areas are designated for addresses storing register information.

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