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HD64F7047 Datasheet(PDF) 173 Page - Renesas Technology Corp |
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HD64F7047 Datasheet(HTML) 173 Page - Renesas Technology Corp |
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173 / 764 page  Rev. 2.00, 09/04, page 133 of 720 Section 9 Bus State Controller (BSC) The bus state controller (BSC) divides up the address spaces and outputs control for various types of memory. This enables memories like SRAM and ROM to be linked directly to the chip without external circuitry. 9.1 Features The BSC has the following features: • Address space is divided into four spaces A maximum linear 256-kbyte bus width (8 bits) for both on-chip ROM enabled mode and on-chip ROM disabled mode, as for address space CS0 Wait states can be inserted by software for each space Wait state insertion with WAIT pin in external memory space access Outputs control signals for each space according to the type of memory connected • On-chip ROM and RAM interfaces On-chip ROM and RAM access of 32 bits in 1 state Figure 9.1 shows the BSC block diagram. |
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