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HD64F7047 Datasheet(PDF) 175 Page - Renesas Technology Corp

Part # HD64F7047
Description  Renesas 32-Bit RISC Microcomputer SuperHTMRISC engine Family/SH7000 Series
PDF  764 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

HD64F7047 Datasheet(HTML) 175 Page - Renesas Technology Corp

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Rev. 2.00, 09/04, page 135 of 720
9.2
Input/Output Pin
Table 9.1 shows the bus state controller pin configuration.
Table 9.1
Pin Configuration
Name
Abbr.
I/O
Description
Address bus
A17 to A0
O
Address output
Data bus
D7 to D0
I/O
8-bit data bus
Chip select
CS0
O
Chip select signal indicating the area being
accessed
Read
RD
O
Strobe that indicates the read cycle
Lower write
WRL
O
Strobe that indicates a write cycle to the lower 8
bits (D7 to D0)
Wait
WAIT
I
Wait state request signal
Bus request
BREQ
I
Bus release request input
Bus acknowledge
BACK
O
Bus use enable output
9.3
Register Configuration
The BSC has four registers. For details on these register addresses and register states in each
processing states, refer to appendix A, Internal I/O Register.
These registers are used to control wait states, bus width, and interfaces with memories like ROM
and SRAM. All registers are 16 bits.
• Bus control register 1 (BCR1)
• Bus control register 2 (BCR2)
• Wait control register 1 (WCR1)
• RAM emulation register (RAMER)



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