HD64F7047 datasheet(242/764 Pages) RENESAS

Part #	HD64F7047

Description	Renesas 32-Bit RISC Microcomputer SuperHTMRISC engine Family/SH7000 Series

PDF	764 Pages

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Manufacturer	RENESAS [Renesas Technology Corp]

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242 / 764 page

Rev. 2.00, 09/04, page 202 of 720

10.4.3

Buffer Operation

Buffer operation, provided for channels 0, 3, and 4, enables TGRC and TGRD to be used as buffer

registers.

Buffer operation differs depending on whether TGR has been designated as an input capture

Table 10.29 shows the register combinations used in buffer operation.

Table 10.29 Register Combinations in Buffer Operation

Channel

Timer General Register

Buffer Register

TGRA_0

TGRC_0

TGRB_0

TGRD_0

TGRA_3

TGRC_3

TGRB_3

TGRD_3

TGRA_4

TGRC_4

TGRB_4

TGRD_4

• When TGR is an output compare register

When a compare match occurs, the value in the buffer register for the corresponding channel is

transferred to the timer general register.

This operation is illustrated in figure 10.13.

Buffer

Timer general

TCNT

Comparator

Compare match signal

Figure 10.13 Compare Match Buffer Operation

HD64F7047 Datasheet(PDF) 242 Page - Renesas Technology Corp