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HD64F7047 Datasheet(PDF) 246 Page - Renesas Technology Corp |
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HD64F7047 Datasheet(HTML) 246 Page - Renesas Technology Corp |
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246 / 764 page  Rev. 2.00, 09/04, page 206 of 720 10.4.4 Cascaded Operation In cascaded operation, two 16-bit counters for different channels are used together as a 32-bit counter. This function works by counting the channel 1 counter clock upon overflow/underflow of TCNT_2 as set in bits TPSC0 to TPSC2 in TCR. Underflow occurs only when the lower 16-bit TCNT is in phase-counting mode. Table 10.30 shows the register combinations used in cascaded operation. Note: When phase counting mode is set for channel 1 or 4, the counter clock setting is invalid and the counters operates independently in phase counting mode. Table 10.30 Cascaded Combinations Combination Upper 16 Bits Lower 16 Bits Channels 1 and 2 TCNT_1 TCNT_2 Example of Cascaded Operation Setting Procedure: Figure 10.18 shows an example of the setting procedure for cascaded operation. Cascaded operation Set cascading Start count <Cascaded operation> [1] [2] [1] Set bits TPSC2 to TPSC0 in the channel 1 TCR to B'1111 to select TCNT_2 overflow/ underflow counting. [2] Set the CST bit in TSTR for the upper and lower channel to 1 to start the count operation. Figure 10.18 Cascaded Operation Setting Procedure |
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