HD64F7047 datasheet(247/764 Pages) RENESAS

247 / 764 page

Rev. 2.00, 09/04, page 207 of 720

Examples of Cascaded Operation: Figure 10.19 illustrates the operation when TCNT_2

overflow/underflow counting has been set for TCNT_1 and phase counting mode has been

designated for channel 2.

TCNT_1 is incremented by TCNT_2 overflow and decremented by TCNT_2 underflow.

TCLKC

TCNT_2

FFFD

TCNT_1

0001

TCLKD

FFFE

FFFF

0000

0001

0002

0001

0000

FFFF

0000

Figure 10.19 Example of Cascaded Operation

10.4.5

PWM Modes

In PWM mode, PWM waveforms are output from the output pins. The output level can be selected

as 0, 1, or toggle output in response to a compare match of each TGR.

TGR registers settings can be used to output a PWM waveform in the range of 0% to 100% duty.

Designating TGR compare match as the counter clearing source enables the period to be set in that

also possible.

There are two PWM modes, as described below.

1. PWM mode 1

PWM output is generated from the TIOCA and TIOCC pins by pairing TGRA with TGRB and

TGRC with TGRD. The output specified by bits IOA0 to IOA3 and IOC0 to IOC3 in TIOR is

output from the TIOCA and TIOCC pins at compare matches A and C, and the output

specified by bits IOB0 to IOB3 and IOD0 to IOD3 in TIOR is output at compare matches B

and D. The initial output value is the value set in TGRA or TGRC. If the set values of paired

TGRs are identical, the output value does not change when a compare match occurs.

In PWM mode 1, a maximum 8-phase PWM output is possible.

HD64F7047 Datasheet(PDF) 247 Page - Renesas Technology Corp