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HD64F7047 Datasheet(PDF) 297 Page - Renesas Technology Corp

Part # HD64F7047
Description  Renesas 32-Bit RISC Microcomputer SuperHTMRISC engine Family/SH7000 Series
PDF  764 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

HD64F7047 Datasheet(HTML) 297 Page - Renesas Technology Corp

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Rev. 2.00, 09/04, page 257 of 720
Status Flag Clearing Timing: After a status flag is read as 1 by the CPU, it is cleared by writing
0 to it. When the DTC is activated, the flag is cleared automatically. Figure 10.68 shows the
timing for status flag clearing by the CPU, and Figure 10.69 shows the timing for status flag
clearing by the DTC.
Status flag
Write signal
Address
TSR address
Interrupt
request signal
TSR write cycle
T1
T2
P
φ
Figure 10.68 Timing for Status Flag Clearing by the CPU
Interrupt
request signal
Status flag
Address
Source address
DTC
read cycle
T1
T2
Destination
address
T1
T2
DTC
write cycle
P
φ
Figure 10.69 Timing for Status Flag Clearing by DTC Activation



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