HD64F7047 datasheet(298/764 Pages) RENESAS

Part #	HD64F7047

Description	Renesas 32-Bit RISC Microcomputer SuperHTMRISC engine Family/SH7000 Series

PDF	764 Pages

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Manufacturer	RENESAS [Renesas Technology Corp]

Direct Link	http://www.renesas.com

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298 / 764 page

Rev. 2.00, 09/04, page 258 of 720

10.7

Usage Notes

10.7.1

Module Standby Mode Setting

MTU operation can be disabled or enabled using the module standby register. The initial setting is

for MTU operation to be halted. Register access is enabled by clearing module standby mode. For

details, refer to section 24, Power-Down Modes.

10.7.2

Input Clock Restrictions

The input clock pulse width must be at least 1.5 states in the case of single-edge detection, and at

least 2.5 states in the case of both-edge detection. The TPU will not operate properly at narrower

pulse widths.

In phase counting mode, the phase difference and overlap between the two input clocks must be at

least 1.5 states, and the pulse width must be at least 2.5 states. Figure 10.43 shows the input clock

conditions in phase counting mode.

Overlap

Phase

differ-

ence

Phase

differ-

ence

Overlap

TCLKA

(TCLKC)

TCLKB

(TCLKD)

Pulse width

Notes: Phase difference and overlap

Pulse width

: 1.5 states or more

: 2.5 states or more

Figure 10.70 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode

HD64F7047 Datasheet(PDF) 298 Page - Renesas Technology Corp