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HD64F7047 Datasheet(PDF) 299 Page - Renesas Technology Corp |
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HD64F7047 Datasheet(HTML) 299 Page - Renesas Technology Corp |
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299 / 764 page  Rev. 2.00, 09/04, page 259 of 720 10.7.3 Caution on Period Setting When counter clearing on compare match is set, TCNT is cleared in the final state in which it matches the TGR value (the point at which the count value matched by TCNT is updated). Consequently, the actual counter frequency is given by the following formula: f = P φ (N + 1) Where f: Counter frequency P φ: Peripheral clock operating frequency N: TGR set value 10.7.4 Contention between TCNT Write and Clear Operations If the counter clear signal is generated in the T2 state of a TCNT write cycle, TCNT clearing takes precedence and the TCNT write is not performed. Figure 10.71 shows the timing in this case. Counter clear signal Write signal Address P φ TCNT address TCNT TCNT write cycle T1 T2 N H'0000 Figure 10.71 Contention between TCNT Write and Clear Operations |
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