7721 datasheet(454/577 Pages) RENESAS

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APPLICATION

7721 Group User’s Manual

16–51

16.2 Examples of using DMA controller

DMA2 mode register L (Address 1FEC16)

Transfer unit : 16 bits

2-bus cycle transfer

Cycle-steal transfer mode

Transfer source address direction : At slow up; “012” (Forward)

At slow down; “102” (Backward)

Transfer destination address direction : Fixed

DMA2 mode register H (Address 1FED16)

Transfer source Wait

No transfer destination Wait

Single transfer mode

! 0

001000

Source address register 2 (Addresses 1FE216 to 1FE016)

Timer A0 set value data table’s start address

b23

b16 b15

b8 b7

Timer A0 register’s address

b23

b16 b15

b8 b7

0016

4616

b23

b16 b15

b8 b7

DMA2 control register (Address 1FEE16)

DMA request source : Timer A0

DMAACK2 pin : Invalid

000

DMA2 interrupt control register (Address 6E16)

Interrupt priority level : any of “0012” to “1112”

Destination address register 2 (Addresses 1FE616 to 1FE416)

Transfer counter register 2 (Addresses 1FEA16 to 1FE816)

Data number of Timer A0 set value data table

! : It may be “0” or “1.”

Fig. 16.2.9 Initial setting example for relevant register (2)

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