7906 datasheet(245/531 Pages) RENESAS

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SERIAL I/O

7906 Group User’s Manual Rev.2.0

11-4

11.2.1 UARTi transmit/receive mode register

Figure 11.2.2 shows the structure of UARTi transmit/receive mode register.

11.2 Block description

Fig. 11.2.2 Structure of UARTi transmit/receive mode register

UART0 transmit/receive mode register (Address 3016)

UART1 transmit/receive mode register (Address 3816)

Serial I/O mode select bits

Internal/External clock select bit

Stop bit length select bit

(Valid in UART mode)

(Note)

Odd/Even parity select bit

(Valid in UART mode when parity

enable bit = “1.”)

(Note)

Parity enable bit

(Valid in UART mode)

(Note)

Sleep select bit

(Valid in UART mode)

(Note)

b7 b6 b5 b4 b3 b2 b1 b0

Note: Bits 4 to 6 are invalid in the clock synchronous serial I/O mode. (They may be either “0” or “1.”) Additionally, fix bit 7 to “0.”

0 0 0 : Serial I/O is invalid.

(P1 functions as a programmable I/O port.)

0 0 1 : Clock synchronous serial I/O mode

0 1 0 :

0 1 1 :

1 0 0 : UART mode (Transfer data length = 7 bits)

1 0 1 : UART mode (Transfer data length = 8 bits)

1 1 0 : UART mode (Transfer data length = 9 bits)

1 1 1 : Do not select.

b2 b1 b0

0 : Internal clock

1 : External clock

0 : One stop bit

1 : Two stop bits

0 : Odd parity

1 : Even parity

0 : Parity disabled

1 : Parity enabled

0 : Sleep mode terminated (Invalid)

1 : Sleep mode selected

Do not select.

Bit name

Bit

Function

At reset

R/W

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