7906 datasheet(249/531 Pages) RENESAS

249 / 531 page

SERIAL I/O

7906 Group User’s Manual Rev.2.0

11-8

11.2 Block description

11.2.3 UARTi transmit/receive control register 1

Figure 11.2.4 shows the structure of UARTi transmit/receive control register 1.

Fig. 11.2.4 Structure of UARTi transmit/receive control register 1

UART0 transmit/receive control register 1 (Address 3516)

UART1 transmit/receive control register 1 (Address 3D16)

Transmit enable bit

Transmit buffer empty flag

Receive enable bit

Receive complete flag

Overrun error flag

Framing error flag

(Note)

(Valid in UART mode)

Parity error flag

(Note)

(Valid in UART mode)

Error sum flag

(Note)

(Valid in UART mode)

b7 b6 b5 b4 b3 b2 b1 b0

0 : Reception disabled

1 : Reception enabled

0 : No data is present in the receive buffer register

1 : Data is present in the receive buffer register

Note: Bits 5 to 7 are invalid in the clock synchronous serial I/O mode.

0 : Transmission disabled

1 : Transmission enabled

0 : Data is present in the transmit buffer register

1 : No data is present in the transmit buffer register

0 : No parity error

1 : Parity error detected

0 : No error

1 : Error detected

0 : No overrun error

1 : Overrun error detected

0 : No framing error

1 : Framing error detected

Bit name

Bit

Function

At reset

R/W

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