7906 datasheet(253/531 Pages) RENESAS

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SERIAL I/O

7906 Group User’s Manual Rev.2.0

11-12

11.2.5 UARTi receive register and UARTi receive buffer register

Figure 11.2.7 shows the block diagram of the receiver; Figure 11.2.8 shows the structure of UARTi receive

buffer register.

11.2 Block description

Fig. 11.2.7 Block diagram of receiver

Clock sync.

PAR

2SP

1SP

UART

RxDi

SP : Stop bit

PAR : Parity bit

8-bit UART

9-bit UART

7-bit UART

9-bit UART

Clock sync.

7-bit UART

8-bit UART

Data bus (even)

Data bus (odd)

UARTi receive register

Parity

enabled

Parity

disabled

UARTi receive

buffer register

Fig. 11.2.8 Structure of UARTi receive buffer register

UART0 receive buffer register (Addresses 3716, 3616)

UART1 receive buffer register (Addresses 3F16, 3E16)

8 to 0

15 to 9

(b15)

(b8)

Receive data is read out from here.

The value is “0” at reading.

Undefined

—

Bit

Function

At reset

R/W

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