7906 datasheet(271/531 Pages) RENESAS

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SERIAL I/O

7906 Group User’s Manual Rev.2.0

11-30

11.3 Clock synchronous serial I/O mode

Fig. 11.3.9 Processing after reception is completed

[When not using interrupts]

[When using interrupts]

A UARTi receive interrupt request occurs

when reception is completed.

UARTi receive interrupt

Processing after reading out receive data

UART0 receive buffer register (Address 3616)

UART1 receive buffer register (Address 3E16)

Reading of receive data (Note 2)

Read out receive data.

Checking completion of reception

Notes 1: When performing the processing after reception is completed, using an interrupt, be sure to

select a receive interrupt (UARTi receive interrupt mode select bit = “0.”)

2: In the case of an external clock and the RTS function selected, the RTSi output level becomes

“L” when the UARTi receive buffer register is read out. Accordingly, when performing reception

continuously, be sure to write the dummy data to the UARTi transmit buffer register before

reading out the UARTi receive buffer register.

3: This figure shows the bits and registers required for the processing.

See Figure 11.3.12 for the change of flag state and the occurrence timing of an interrupt request.

Checking error

Overrun error flag

0 : No overrun error

1 : Overrun error detected

UART0 transmit/receive control register 1 (Address 3516)

UART1 transmit/receive control register 1 (Address 3D16)

UART0 transmit/receive control register 1 (Address 3516)

UART1 transmit/receive control register 1 (Address 3D16)

Receive complete flag

0 : Reception not completed

1 : Reception completed

(Note 1)

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