7906 datasheet(274/531 Pages) RENESAS

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SERIAL I/O

7906 Group User’s Manual Rev.2.0

11-33

11.3 Clock synchronous serial I/O mode

Fig. 11.3.11 Receive operation

Fig. 11.3.12 Example of receive timing (when external clock selected)

UARTi receive register

Receive data

MSB

LSB

Transfer clock output from

or input to CLKi pin (Note).

UARTi receive buffer register

•

Note: This applies when the CLK polarity select bit = “0.”

When the CLK polarity select bit = “1,” data is shifted at the rising edge of

the transfer clock.

The above timing diagram applies when the following

conditions are satisfied:

q External clock selected

q RTS function selected

q CLK polarity select bit = “0”

fEXT: Frequency of external clock

D2 D3

D4 D5 D6

D1 D2

1/fEXT

RTSi

CLKi

RxDi

When the CLKi pin’s input level is “H,” be sure to sati

the following conditions:

q Writing of dummy data to UARTi transmit buffer re

q Transmit enable bit = “1”

q Receive enable bit = “1”

Receive enable bit

Transmit enable bit

Transmit buffer

empty flag

Dummy data is set to UARTi transmit buffer register.

UARTi transmit register

←UARTi transmit buffer

Receive data is taken in.

UARTi receive register

→UARTi receive buffer register

UARTi receive buffer register is read o

Receive complete flag

UARTi receive

interrupt request bit

Cleared to “0” when interrupt request is accepted or

cleared to “0” by software.

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