7906 datasheet(272/531 Pages) RENESAS

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SERIAL I/O

7906 Group User’s Manual Rev.2.0

11-31

11.3 Clock synchronous serial I/O mode

11.3.6 Receive operation

In the case of an internal clock selected, when the receive conditions described in section “11.3.5 Method

of reception” have been satisfied, a transfer clock is generated and the reception is started after 1 cycle

of the transfer clock or less has passed. In the case of an external clock selected, when the receive

conditions have been satisfied, the UARTi enters the receive-enabled state, and then reception will be

started when an external clock is input to the CLKi pin.

In the case of an external clock selected, when connecting the RTSi pin to the CTSi pin of the transmitter

side, the timing of transmission and that of reception can be matched. In the case of an internal clock

selected, do not use the RTS function. It is because the RTS output is undefined in the case of an internal

clock selected.

In the case of an external clock and the RTS function selected, the RTSi pin’s output level becomes as

described below.

When the receive enable bit = “0,” if one of the following is performed, the RTSi pin’s output level becomes

“L” and informs of the transmitter side that reception has become enabled:

• The receive enable bit is set to “1.”

• The low-order byte of the UARTi receive buffer register is read out.

When the receive enable bit = “1,” if the low-order byte of the UARTi receive buffer register is read out,

the RTSi pin’s output level becomes “L.”

Accordingly, when performing reception continuously, an overrun occurrence can be avoided because the

RTS output level does not become “L” until the receive data is read out.

When reception has started, the RTSi pin’s output level becomes “H.”

Figure 11.3.10 shows a connection example.

Fig. 11.3.10 Connection example

TxDi

RxDi

CLKi

TxDi

RxDi

CLKi

Transmitter side

Receiver side

CTSi

RTSi

7906 Datasheet(PDF) 272 Page - Renesas Technology Corp