7906 datasheet(273/531 Pages) RENESAS

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SERIAL I/O

7906 Group User’s Manual Rev.2.0

11-32

11.3 Clock synchronous serial I/O mode

The receive operations are described below:

➀ The signal input to the RxDi pin is taken into the most significant bit of the UARTi receive register

synchronously with the valid edge✼ of the clock output from the CLKi pin or input to the CLKi pin.

➁ The contents of the UARTi receive register are shifted, bit by bit, to the right.

➂ Steps ➀ and ➁ are repeated at each valid edge of the clock output from the CLKi pin or input to the

CLKi pin.

➃ When 1-byte data has been prepared in the UARTi receive register, the contents of this register are

transferred to the UARTi receive buffer register.

➄ Simultaneously with step ➃, the receive complete flag is set to “1.” Additionally, when the receive

interrupt is selected (UARTi receive interrupt mode select bit = “0”), a UARTi receive interrupt request

occurs and its interrupt request bit is set to “1.”

Valid edge✼ : A rising edge is selected when the CLK polarity select bit = “0.”

A falling edge is selected when the CLK polarity select bit = “1.”

The receive complete flag is cleared to “0” when the low-order byte of the UARTi receive buffer register

is read out. Figure 11.3.11 shows the receive operation, and Figure 11.3.12 shows an example of receive

timing (when an external clock is selected).

When the transfer format select bit is “1” (MSB first), each bit’s position of this register’s contents is

reversed, and then the resultant data is read out.

7906 Datasheet(PDF) 273 Page - Renesas Technology Corp