7906 datasheet(269/531 Pages) RENESAS

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SERIAL I/O

7906 Group User’s Manual Rev.2.0

11-28

11.3 Clock synchronous serial I/O mode

11.3.5 Method of reception

Figure 11.3.8 shows an initial setting example for relevant registers when receiving. Reception is started

when all of the following conditions (➀ to ➂) have been satisfied. When an external clock is selected,

satisfy conditions ➀ to ➂ with the following preconditions satisfied.

The CLKi pin’s input is at “H” level (External clock selected, when the CLK polarity select bit = “0” ).

The CLKi pin’s input is at “L” level (External clock selected, when the CLK polarity select bit = “1”).

Note: When an internal clock is selected, the above preconditions are ignored.

➀ Dummy data is present in the UARTi transmit buffer register (transmit buffer empty flag = “0”)

➁ Reception is enabled (receive enable bit = “1”).

➂ Transmission is enabled (transmit enable bit = “1”).

By connecting the RTSi pin (receiver side) and CTSi pin (transmitter side), the timing of transmission and

that of reception can be matched. For details, refer to section “11.3.6 Receive operation.”

When using interrupts, it is necessary to set the relevant registers to enable interrupts. For details, refer

to “CHAPTER 6. INTERRUPTS.”

Figure 11.3.9 shows processing after reception is completed.

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