7906 datasheet(267/531 Pages) RENESAS

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SERIAL I/O

7906 Group User’s Manual Rev.2.0

11-26

11.3 Clock synchronous serial I/O mode

11.3.4 Transmit operation

When the transmit conditions described in section “11.3.3 Method of transmission” have been satisfied

in the case of an internal clock selected, a transfer clock is generated and the following operations are

automatically performed after 1 cycle of the transfer clock or less has passed. In the case of an external

clock selected, when the transmit conditions have been satisfied and then an external clock is input to the

CLKi pin, the following operations are automatically performed:

•The UARTi transmit buffer register’s contents are transferred to the UARTi transmit register.

•The transmit buffer empty flag is set to “1.”

•The transmit register empty flag is cleared to “0.”

•8 transfer clocks are generated (in the case of an internal clock selected).

•A UARTi transmit interrupt request occurs, and the interrupt request bit is set to “1.”

The transmit operations are described below:

➀ Data in the UARTi transmit register is transmitted from the TxDi pin synchronously with the valid edge✼

of the clock output from or input to the CLKi pin.

➁ This data is transmitted, bit by bit, sequentially beginning with the least significant bit.

➂ When 1-byte data has been transmitted, the transmit register empty flag is set to “1.” This indicates the

completion of transmission.

Valid edge✼ : A falling edge is selected when the CLK polarity select bit = “0.”

A rising edge is selected when the CLK polarity select bit = “1.”

Figure 11.3.5 shows the transmit operation.

When an internal clock is selected, if the transmit conditions for the next data are satisfied at completion

of the transmission, the transfer clock is generated continuously. Accordingly, when performing transmission

continuously, set the next transmit data to the UARTi transmit buffer register during transmission (when the

transmit register empty flag = “0”). When the transmit conditions for the next data are not satisfied, the

transfer clock stops at “H” level (when the CLK polarity select bit = “0”), or “L” level (when the CLK polarity

select bit = “1”).

Figures 11.3.6 and 11.3.7 show examples of transmit timing.

Fig. 11.3.5 Transmit operation

Transfer clock output from

or input to the CLKi pin (Note)

UARTi transmit buffer register

Transmit data

MSB

LSB

UARTi transmit register

Note: This applies when the CLK polarity select bit = “0.”

When the CLK polarity select bit = “1,” data is shifted at the rising edge of the transfer clock.

•

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