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7906 Datasheet(PDF) 263 Page - Renesas Technology Corp |
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7906 Datasheet(HTML) 263 Page - Renesas Technology Corp |
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263 / 531 page ![]() SERIAL I/O 7906 Group User’s Manual Rev.2.0 11-22 11.3 Clock synchronous serial I/O mode 11.3.2 Transfer data format LSB first or MSB first can be selected as the transfer data format. Table 11.3.3 lists the relationship between the transfer data format and writing/reading to and from the UARTi transmit/receive buffer register. The transfer format select bit (bit 7 at addresses 3416, 3C16) selects the transfer data format. When this bit is cleared to “0,” the set data is written to the UARTi transmit buffer register as the transmit data, as it is. Similarly, the data in the UARTi receive buffer register is read out as the receive data, as it is. (See the upper row in Table 11.3.3.) When this bit is set to “1,” each bit’s position of set data is reversed, and the resultant data will be written to the UARTi transmit buffer register as the transmit data. Similarly, each bit’s position of data in the UARTi receive buffer register is reversed, and the resultant data will be read out as the receive data. (See the lower row in Table 11.3.3.) Note that only the method of writing/reading to and from the UARTi transmit/receive buffer register is affected by selection of the transfer data format, and that the transmit/receive operation is unaffected by it. Table 11.3.3 Relationship between transfer data format and writing/reading to and from UARTi transmit/ receive buffer register Writing to UARTi transmit buffer register Reading from UARTi receive buffer register Data bus UARTi transmit buffer register DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Data bus UARTi receive buffer register DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 LSB (Least Significant Bit) first Data bus UARTi transmit buffer register D7 D6 D5 D4 D3 D2 D1 D0 Data bus UARTi receive buffer register MSB (Most Significant Bit) first Transfer data format Transfer format select bit 0 1 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 |
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