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SERIAL I/O

7906 Group User’s Manual Rev.2.0

11-19

11.2.10 CTS/RTS function

When the CTS function is selected, the signal input to the CTSi pin must be at “L” level. (This is one of

the transmit conditions.)

When the RTS function is selected, the RTSi pin outputs the following signals:

(1)

Clock synchronous serial I/O mode

When the receive enable bit (bit 2 at addresses 3516, 3D16) = “0” (reception disabled), the RTSi pin

outputs “H” level.

When the receive enable bit = “0” (reception disabled), the RTSi pin outputs “L” level by setting the

receive enable bit to “1,” or by reading the low-order byte of the UARTi receive buffer register.

When the receive enable bit = “1” (continuously reception), the RTSi pin outputs “L” level by reading

the low-order byte of the UARTi receive buffer register.

When reception has started, the RTSi pin outputs “H” level.

When an internal clock is selected (bit 3 at addresses 3016, 3816 = “0”), do not select the RTS function

because the RTS output is undefined.

(2)

UART mode

When the receive enable bit (bit 2 at addresses 3516, 3D16) = “0” (reception disabled), the RTSi pin

outputs “H” level.

When the receive enable bit = “0” (reception disabled), the RTSi pin outputs “L” level by setting the

receive enable bit to “1,” or by reading the low-order byte of the UARTi receive buffer register.

When the receive enable bit = “1” (continuously reception), the RTSi pin outputs “L” level by reading

the low-order byte of the UARTi receive buffer register.

When reception has started, the RTSi pin outputs “H” level.

Selection of the CTS/RTS function depends on the following bits.

•CTS/RTS function select bit (bit 2 at addresses 3416, 3C16: see Figure 11.2.3.)

•CTS/RTS enable bit (bit 4 at addresses 3416, 3C16: see Figure 11.2.3.)

•CTS0/RTS0 separate select bit (bit 0 at address AC16: see Figure 11.2.13.)

•CTS1/RTS1 separate select bit (bit 1 at address AC16: see Figure 11.2.13.)

Table 11.2.1 lists the selection of the CTS/RTS function.

11.2 Block description

✕: It may be either “0” or “1.”

Notes 1: When using the P11 or P15 pin as the CTSi pin, be sure to clear the corresponding bit of the port

P1 direction register to “0.”

2: When CTSi/RTSi separation is selected, the CLKi pin cannot be used. Accordingly, CTSi/RTSi

cannot be separated in the clock synchronous serial I/O mode. When separating CTSi/RTSi in

UART mode, be sure to select an internal clock.

Table 11.2.1 Selection of CTS/RTS function

CTS/RTS

enable bit

Functions

CTSi/RTSi

separate select bit

CTS/RTS

function select bit P10/CTS0/RTS0 pin

CTS0

RTS0

P10

P11 or CLK0

CTS0 (Notes 1, 2)

P11 or CLK0

P11/CTS0/CLK0 pin P14/CTS1/RTS1 pin

CTS1

RTS1

P14

P15 or CLK1

CTS1 (Notes 1, 2)

P15 or CLK1

P15/CTS1/CLK1 pin

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