7906 datasheet(261/531 Pages) RENESAS

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SERIAL I/O

7906 Group User’s Manual Rev.2.0

11-20

11.3 Clock synchronous serial I/O mode

Table 11.3.1 lists the performance overview in the clock synchronous serial I/O mode, and Table 11.3.2 lists

the functions of I/O pins in this mode.

Table 11.3.1 Performance overview in clock synchronous serial I/O mode

Item

Transfer data format

Transfer rate

Transmit/Receive control

When selecting internal clock

When selecting external clock

Functions

Transfer data has a length of 8 bits.

LSB first or MSB first can be selected by software.

BRGi’s output divided by 2

Maximum 5 Mbps

CTS function or RTS function can be selected by software.

Table 11.3.2 Functions of I/O pins in clock synchronous serial I/O mode

Functions

Serial data output pin

Programmable I/O port pin

Serial data input pin

Programmable I/O port pin

Transfer clock output pin

Transfer clock input pin

CTS input pin

RTS output pin

Programmable I/O port

Pin name

TxDi (P13, P17)

RxDi (P12, P16)

CLKi (P11, P15)

CTSi, RTSi

(P10, P11, P14, P15)

Method of selection

TxD0/P13 or TxD1/P17 switch bit = “0”

(Dummy data is output when performing only reception.) (Note)

TxD0/P13 or TxD1/P17 switch bit = “1”

Port P1 direction register’s corresponding bit = “0”

– (Can be used as an I/O port pin when performing only transmission.)

Internal/External clock select bit = “0”

Internal/External clock select bit = “1”

See Table 11.2.1.

Port P1 direction register: address 0516

Internal/External clock select bit: bit 3 at addresses 3016, 3816

TxD0/P13 switch bit: bit 2 at address AC16

TxD1/P17 switch bit: bit 3 at address AC16

Note: The TxDi pin outputs “H” level until transmission starts after UARTi’s operating mode is selected.

11.3.1 Transfer clock (Synchronizing clock)

Data transfer is performed synchronously with a transfer clock. For the transfer clock, the following selection

is possible:

q Whether to generate a transfer clock internally or to input it from the external.

q Polarity of transfer clock.

The transfer clock is generated by operation of the transmit control circuit. Accordingly, even when performing

only reception, set the transmit enable bit to “1,” and set dummy data in the UARTi transmit buffer register

in order to make the transmit control circuit active.

(1)

Internal generation of transfer clock

The count source selected with the BRG count source select bits is divided by the BRGi, and the

BRGi output is further divided by 2. This divided output is the transfer clock. The transfer clock is

output from the CLKi pin.

Transfer clock’s frequency =

fi: Frequency of BRGi’s count source (f2, f16, f64, or f512)

n: Setting value of BRGi

2 (n+1)

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