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TSS463B Datasheet(PDF) 16 Page - ATMEL Corporation

Part # TSS463B
Description  VAN Data Link Controller with Serial Interface
PDF  59 Pages
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Manufacturer  ATMEL [ATMEL Corporation]
Direct Link  http://www.atmel.com
Logo ATMEL - ATMEL Corporation

TSS463B Datasheet(HTML) 16 Page - ATMEL Corporation

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TSS463B
4102E–AUTO–12/04
Figure 14. Framing Sequences
When the complete SOF sequence has been transmitted or received, the circuit will
start the transmission or reception of the identifier field.
All data on the VAN bus, including the identifier and Frame Check Sum (FCS), are
transmitted using enhanced Manchester code.
In enhanced Manchester code, three NRZ bits are transmitted first followed by one
Manchester bit, then three more NRZ bits followed by one Manchester bit and so on.
Since the high state is recessive and the low state is dominant, the bus arbitration can
be done. If a module wants access to the bus, it must first listen to the bus during one
full End of Frame (EOF) and one full Inter Frame Spacing (IFS) period to determine
whether the bus is free or not (i.e. no dominant states received).
Figure 15. Data Encoding
The IFS is defined to be a minimum of 64 prescaled clock periods. The TSS463B,
accepts an IFS of zero prescaled clocks for the reception only of a SOF sequence.
Once the bus has been determined as being free, the module must, if it is an autono-
mous module, emit an SOF sequence or, if it is a synchronous access module, wait until
it detects a preamble sequence.
VAN BUS
SEQUENCE
VAN BUS
SEQUENCE
NUMBER OF
PRESCALED
CLOCKS
PREAMBLE
START OF FRAME
START
SYNC
END OF
DATA
ACK
END OF FRAME
0
16
32
48
64
80
96 112 128 144 160 176 192
VAN BUS
SEQUENCE
VAN BUS
SEQUENCE
VAN BUS
SEQUENCE
NUMBER OF
PRESCALED
CLOCKS
NRZ 0
NRZ 1
MANCHESTER 0
MANCHESTER 1
0
8
16
24
32



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