TSS463B datasheet(27/59 Pages) ATMEL

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TSS463B

4102E–AUTO–12/04

Control and Status Registers

Line Control Register (0x00)

•

Read/write register.

•

Default value after reset: 0

×00

•

Reserved: Bit 2, this bit must not be set by the user; a 0 must always be written to

this bit.

CD[3:0]:Clock Divider

They control the VAN Bus rate through a Baud Rate generator according to the formula

below:

PC: Pulsed Code

One: The TSS463B will transmit and receive data using the pulsed coding mode (i.e

optical or radio link mode). The use of this mode implies communication via the RxD0

input and the non-functionality of the diagnosis system.

Zero: (default at reset) The TSS463B will transmit and receive data using the Enhanced

Manchester code. (RxD0, RxD1, RxD2 used).

IVTX: Invert TxD output

IVRX: Invert RxD inputs

The user can invert the logical levels used on either the TxD output or the RxD inputs in

order to adapt to different line drivers and receivers.

One: A one on either of these bits will invert the respective signals.

Zero: (default at reset) The TSS463B will set TxD to recessive state in Idle mode and

consider the bus free (recessive states on RxD inputs).

Transmit Control Register

(0x01)

•

Read/Write register.

•

Default value after reset: 0x02

MR[3:0]: Maximum Retries

These bits allow the user to control the amount of retries the circuit will perform if any

errors occurred during transmission.

7654

3210

CD3

CD2

CD1

CD0

IVTX

IVRX

fTSCLK

()

fXTAL1

()

n 16

-------------------------

7654

3210

MR3

MR2

MR1

MR0

VER2

VER1

VER0

TSS463B Datasheet(PDF) 27 Page - ATMEL Corporation

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