TSS463B datasheet(29/59 Pages) ATMEL

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TSS463B

4102E–AUTO–12/04

•

In the two low order bits, the user controls if the SDC and TIP are to be generated

automatically ETIP, ESDC.

SDC [3:0]: SDC Divider

The input clock is the timeslot clock.

Table 6. System Diagnosis Clock Divider

Ma, Mb: Operating Mode

Command Bits

Table 7. Diagnosis System Command Bits

SDC DIVIDER SDC [3:0]

Divide by

0000

0001

128

0010

256

0011

512

0100

1024

0101

2048

0110

4096

0111

8192

1000

16384

1001

32768

1010

65536

1011

131072

1100

262144

1101

524288

1110

1048576

1111

2097152

SDC calculation: (see “SDC Signal (Synchronous Diagnosis Clock)” on page 24).

Notes:

1. For each module, determine the largest interframe spacing, LIFS (*).

2. For the whole network, get the maximum LIFS, MAX-LIFS.

3. SDC period > MAX-LIFS.

(*) IFS min. = 4 TS

Example: For VAN frame speed rate = 62,5 KTS/s (1 TS = 16 µs), SDC >100 ms

=> 100 ms / 16 µs = 6250, divider chosen: 8192, SDC [3:0] = 0111.

Forces the Communication on RxD0 (differential)

Forces the Communication on RxD2 (DATA)

Forces the Communication on RxD1 (DATA)

Automatic selection

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