TMS320VC5504 datasheet(21/128 Pages) TI

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TMS320VC5504

Fixed-Point Digital Signal Processor

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SPRS609A – JUNE 2009 – REVISED JULY 2009

Table 3-5. Oscillator/PLL Terminal Functions

SIGNAL

TYPE(1)

OTHER(2)(3)

DESCRIPTION

NAME

NO.

DSP clock output signal. For debug purposes, the CLKOUT pin can be used to tap

different clocks within the DSP clock generator. The SRC bits in the CLKOUT

Control Source Register (CCSSR) can be used to specify the CLKOUT pin source.

Additionally, the slew rate of the CLKOUT pin can be controlled by the Output

Slew Rate Control Register (OSRCR) [0x1C16]. For more detailed information on

the CCSSR and OSRCR registers, see the TMS320VC5505 DSP System User's

–

Guide (literature number: SPRUFP0)

CLKOUT

O/Z

DVDDIO

The CLKOUT pin is enabled/disabled through the CLKOFF bit in the CPU ST3_55

reset the CLKOUT pin is enabled until the beginning of the boot sequence, when

the on-chip Bootloader sets CLKOFF = 1 and the CLKOUT pin is disabled (Hi-Z).

For more information on the ST3_55 register, see the TMS320C55x 3.0 CPU

Reference Guide (literature number: SWPU073).

Input clock. This signal is used to input an external clock when the 32-KHz on-chip

oscillator is not used as the DSP clock (pin CLK_SEL = 1). For boot purposes, the

CLKIN frequency is assumed to be either 11.2896, 12, or 12.288 MHz.

The CLK_SEL pin (C7) selects between the 32-KHz crystal clock or CLKIN.

When the CLK_SEL pin is low, this pin should be tied to ground (VSS). When

–

CLKIN

CLK_SEL is high, this pin should be driven by an external clock source.

DVDDIO

If CLK_SEL is high, this pin is used as the reference clock for the clock generator

and during bootup the bootloader bypasses the PLL and assumes the CLKIN

frequency is one of the following frequencies: 11.2896-, 12-, or 12.288-MHz. With

these frequencies in mind, the bootloader sets the SPI clock rates at 500 KHz, the

I2C clock rate at 400 KHz, and UART at 57600 baud.

Clock input select. This pin selects between the 32-KHz crystal clock or CLKIN.

0 = 32-KHz on-chip oscillator drives the RTC timer and the DSP clock generator

while CLKIN is ignored.

–

1 = CLKIN drives the DSP clock generator and the 32-KHz on-chip oscillator

CLK_SEL

DVDDIO

drives only the RTC timer.

This pin is not allowed to change during device operation; it must be tied high or

low at the board.

see Section 5.2,

VDDA_PLL

C10

PWR

1.3-V Analog PLL power supply for the system clock generator.

ROC

see Section 5.2,

VSSA_PLL

GND

Analog PLL ground for the system clock generator.

ROC

(1)

I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal

(2)

IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external

pullup/pulldown resistors are required, see Section 4.8.1, Pullup/Pulldown Resistors.

(3)

Specifies the operating I/O supply voltage for each signal

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