ST7567

Ver 1.4b

39/49

2009/02/04

(VDD1 = 1.8V , Ta =25

Item

Signal

Symbol

Condition

Min.

Max.

Unit

Address setup time

tAW8

0

—

Address hold time

A0

tAH8

0

—

System cycle time

tCYC8

640

—

/WR L pulse width (WRITE)

tCCLW

360

—

/WR H pulse width (WRITE)

/WR

tCCHW

280

—

/RD L pulse width (READ)

tCCLR

360

—

/RD H pulse width (READ)

RD

tCCHR

280

WRITE Data setup time

tDS8

80

—

WRITE Data hold time

tDH8

20

—

READ access time

tACC8

CL = 16 pF

—

240

READ Output disable time

D[7:0]

tOH8

CL = 16 pF

10

200

ns

*1 The input signal rise time and fall time (tr, tf) is specified at 15 ns or less. When the system cycle time is extremely fast,

(tr + tf) ≦ (tCYC8 – tCCLW – tCCHW) for (tr + tf) ≦ (tCYC8 – tCCLR – tCCHR) are specified.

*2 All timing is specified using 20% and 80% of VDD1 as the reference.

*3 tCCLW and tCCLR are specified as the overlap between CSB being “L” and WR and RD being at the “L” level.