ST7567

Ver 1.4b

13/49

2009/02/04

4-line SPI interface (PSB=“L”, C86=“H” or “L”)

When ST7567 is active (CSB=“L”), serial data (SDA) and serial clock (SCLK) inputs are enabled. When ST7567 is not

active (CSB=“H”), the internal 8-bit shift register and 3-bit counter are reset. Serial data on SDA is latched at the rising edge

of serial clock on SCLK. After the 8

selection pin (A0), which is latched at the 8

parallel data will be display data when A0 is “H” and will be instruction when A0 is “L”. The read feature is not available in

this mode. The DDRAM column address pointer will be increased by one automatically after each byte of DDRAM access.

Please note that the SCLK signal quality is very important and external noise maybe causes unexpected data/instruction

latch.

Fig 4.

4-Line SPI Access

Note:

Some MPU will set the interface to be Hi-Z (high impedance) mode when power saving mode or after hardware reset.

This is not allowed when the VDD1of ST7567 is turned ON. Because the floating input (especially for those control

pins such as CSB, RSTB, RWR or ERD…) maybe cause abnormal latch and cause abnormal display.