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ST7577 Datasheet(PDF) 32 Page - Sitronix Technology Co., Ltd. |
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ST7577 Datasheet(HTML) 32 Page - Sitronix Technology Co., Ltd. |
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32 / 48 page ![]() ST7577 Ver 1.0a 32/48 2008/02/14 Power Saving flow with built-in power circuits ENTERING THE POWER SAVE MODE The power save mode is achieved by setting PD bit to be “1”. No specified instruction flow required. EXITING THE POWER SAVE MODE Figure 21 Exiting Power Save Mode INTERNAL SEQUENCE of EXIT POWER SAVE MODE After receiving the “PD” is “L”, the internal circuits (Power and COM/SEG) will starts the following procedure. Data /WR PD= “L” Booster Regulator Follower COM, SEG t FON t DON t BON t RON Vss Max: 100ms Max: 100ms Max: 100ms Min: 160ms Max: 240ms Note: 1. The power stable time is determined by LCD panel loading. 2. The power stable time in this figure is base on: LCD Panel Size = 1.4 ” with C1=1uF. |
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