ST7577 datasheet(33/48 Pages) SITRONIX

33 / 48 page

ST7577

Ver 1.0a

33/48

2008/02/14

Power OFF flow with built-in power circuits

USING PD BIT

By setting PD=

”H”, ST7577 will go into power save mode. The LCD driving outputs are all fixed to VSS and the built-in power

circuits are turned OFF. After the built-in power circuits are turned OFF, the power (VDD and VDD2) can be removed.

Instruction Flow

Note:

tIPOFF: Internal Power discharge time. => 250ms (max).

tV2OFF: Period between VDD and VDD2 OFF time. => 50 ms (max).

It is NOT recommended to turn VDD OFF before VDD2. Without VDD, the internal status cannot be guaranteed and

internal discharge-process maybe stopped. The un-discharged power maybe polarizes the liquid crystal in panel.

IC will NOT be damaged if either VDD or VDD2 is OFF while another is ON.

The timing is dependent on panel loading and the external capacitor(s).

The timing in these figures is base on the condition that: LCD Panel Size = 1.5

” with C1=1uF, C2=1uF.

Reset Low time after VDD2 is stable.

When turning VDD2 OFF, the falling time should follow the specification:

300ms

≤ tPFall ≤ 1sec

ST7577 Datasheet(PDF) 33 Page - Sitronix Technology Co., Ltd.