ST7577

Ver 1.0a

13/48

2008/02/14

PS2=

“L”, PS1=“L”, PS0=“L”: 4-line SPI interface

When ST7577 is set into 4-line SPI interface mode, setting CSB to be

“L” will active this chip. If CSB is “H”, the internal 8-bit

shift register and a 3-bit counter are reset. When CSB is

“L”, the serial data (SDA) and the serial clock (SCLK) are set into

input mode. The input signal on SDA will be latched into the shift register from D7 to D0 at the rising edge of the serial clock.

The display data/instruction indication is controlled via the register select pin: A0. If A0=

”L”, the input signal on SDA will be

treated as instruction; if A0=

”H”, the input signal on SDA will be treated as data. After 8-bit data are written into the Data

Display RAM, the DDRAM column address pointer will be increased by one automatically.

PS2=

“H”, PS1=“L”, PS0=“L”: 3-line SPI interface

Because 3-line SPI interface mode does not have a register selection pin

“A0”, this mode latches the A0 bit first and then

latches 8-bit input (please refer to the following figure).

Figure 3

3-line SPI Timing

Figure 2

4-line SPI Timing