ST7577 datasheet(10/48 Pages) SITRONIX

10 / 48 page

ST7577

Ver 1.0a

10/48

2008/02/14

LCD DRIVER CLOCK SUPPLY

OSC

When the on-chip oscillator is used, this input must be connected to

VDD. An external clock signal, if used, is connected to this pin. The

oscillator and external clock are both inhibited by connecting the OSC pin

to VSS and the display is not clocked and may be left in a DC state. To

avoid this, the chip should always be put into Power Down Mode before

stopping the clock.

POWER SUPPLY PIN

VSS

Power

Ground.

VDD

Power

Digital Supply voltage.

The 2 supply rails, VDD and VDD2 , could be connected together (for single

power).

If a Digital Option pin is high, must be this level.

VDD2

Power

Analog Supply voltage.

The 2 supply rails, VDD and VDD2 , could be connected together (for single

power).

VRS

Power

Reference voltage. Must be left open.

V0I, V0O, V0S

Power

Positive LCD driving voltage for commons.

V0I is the V0 power source for the LCD driver. If using external V0, apply

the external power source on these pads.

V0O is the internal V0 regulator output pad.

V0S is the feedback for the internal V0 voltage compensation circuit.

They should be separate in ITO and be connected together by FPC.

XV0I, XV0O,XV0S

Power

Negative LCD driving voltage for commons.

XV0I is the XV0 power source for the LCD driver. If using external XV0,

apply the external power source on these pads.

XV0O is the internal XV0 regulator output pad.

XV0S is the feedback for the internal XV0 voltage compensation circuit.

They should be separate in ITO and be connected together by FPC.

VGI, VGO, VGS

Power

LCD driving voltage for segments.

VGI is the VG power source for the LCD driver. If using external VG, apply

external power source on these pads.

VGO is the internal VG regulator output pad.

VGS is the feedback for the internal VG voltage compensation circuit.

They should be separate in ITO and be connected together by FPC.

Power

LCD driving voltage for commons.

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