ST7577 datasheet(9/48 Pages) SITRONIX

9 / 48 page

ST7577

Ver 1.0a

9/48

2008/02/14

RWR_A

(for Port-A)

RWR_B

(for Port-B)

Read/Write execution control pin (PS[0:1]=[L:H]).

PS2

MPU type

RWR

Description

6800-series

R/W

Read/Write control input pin

R/W=

“H”: read;

R/W=

“L”: write.

8080-series

/WR

Write enable clock input pin

The data on D0 to D7 are latched at

the rising edge of the /WR signal.

When in the serial interface, left it connected to VDD.

* MODE pin will select one of two RWR pins. The unused one should be

left floating.

ERD_A

(for Port-A)

ERD_B

(for Port-B)

Read/Write execution control pin (PS[0:1]=[L:H]).

PS2

MPU Type

/RD(E)

Description

6800-series

Read/Write control input pin

R/W=

“H”: When E is “H”, D0 to D7

are in an output status;

R/W=

“L”: The data on D0 to D7 are

latched at the falling edge of the E

signal.

8080-series

/RD

Read enable clock input pin.

When /RD is

“L”, D0 to D7 are in an

output status.

When in the serial interface, left it connected to VDD.

* MODE pin will select one of two RWR pins. The unused one should be

left floating.

When using 8-bit parallel interface: 6800, 8080

8-bit bi-directional data bus that is connected to the standard 8-bit

microprocessor data bus.

When chip select is not active, D0 to D7 is high impedance.

When using serial interface: 4-LINE

D0: serial input clock (SCLK);

D1, D2, D3: serial input data (SDA), must be connected together;

D4~D7 must be connected to VDD (not used).

When chip select is not active, D0 to D7 is high impedance.

D7_A

…D0_A

(for Port-A)

D7_B

…D0_B

(for Port-B)

I/O

When using serial interface: 3-LINE

D0: serial input clock (SCLK).

D1, D2, D3: serial input data (SDA), must be connected together;

D4~D7 must be connected to VDD (not used).

When chip select is not active, D0 to D7 is high impedance.

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