ST7577

Ver 1.0a

38/48

2008/02/14

15. TIMING CHARACTERISTICS

System Bus Read/Write Characteristics (For the 8080 Series MPU)

Figure 23

Rating

Item

Signal

Symbol

Condition

Min.

Typ.

Max.

Units

Address setup time

15

Address hold time

A0

10

System cycle time

150

/WR low pulse width

80

/WR high pulse width

/WR

70

/RD low pulse width

243

/RD high pulse width

/RD

70

WRITE Data setup time

30

WRITE Data hold time

35

READ access time

30

243

READ output disable time

D0 ~ D7

70

ns

*1 The input signal rise time and fall time (tr, tf) is specified at 15 ns or less. When the system cycle time is extremely fast,

(tr +tf) ≦ (tCYC8

– tCCLW – tCCHW) for (tr + tf) ≦ (tCYC8 – tCCLR – tCCHR) are specified.

*3 tCCLW and tCCLR are specified as the overlap between CSB being

“L” and WR and RD being at the “L” level.