ST7577 datasheet(11/48 Pages) SITRONIX

11 / 48 page

ST7577

Ver 1.0a

11/48

2008/02/14

CONFIGURATION PIN

MLB

Data format (MSB on top or LSB on top).

MLB=

”H”, MSB on top (D7 on top);

MLB=

”L”, LSB on top (D0 on top).

DTY

Duty selection pin. Please refer to Page11 for detail output Map.

DTY=

”L”, 1/39 duty;

DTY=

”H”, 1/12 duty.

Set power mode. This pin will change the V0 (Vop) formula parameter.

V0=( a + VOP[6:0] x b )

PM=

”L”, a=3.0V, b=0.03V;

PM=

”H”, a=4.5V, b=0.03V.

MODE

Select MPU interface Port-A (left side) or Port-B (right side).

MODE=

”L”, use Port-A (Port-B should be floating).

MODE=

”H”, use Port-B (Port-A should be floating).

TEST PIN

T0~T9

Test

T0~T8 left them open.

T9 must connect to VDD.

ST7577 has 2 sets of interface port (Port-A & Port-B). These two ports can be selected by

“MODE” pin.

Port-A and Port-B are identical (CSB, A0, /RW, /RD, D7~D0) except RESB pin.

The unused pins should be left floating.

The Microprocessor Interface pins should not be left floating under any operation mode.

Recommend I/O pins ITO Resistance Limitation

Pin Name

ITO Resistance

VRS, T[8:0]

Floating

VSS

<100Ω

VDD

<100Ω

VDD2

<100Ω

V0 (V0I + V0O + V0S), XV0 (XV0I + XV0O + XV0S), VG (VGI + VGO + VGS), VM

<500Ω

CSB, A0, /RD, /WR, D[7:0]

<1KΩ

PS[2:0], OSC

*1, MLB, DTY, MODE, T9

<5KΩ

RESB

<10KΩ

Notes:

If using internal clock, OSC is connect to VDD and the limitation of ITO resistance will be “No Limitation”.

If using external clock, the ITO resistance of OSC should be kept lower than 500

Ω to keep the clock signal quality.

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