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MAC7200 Datasheet(PDF) 322 Page - Freescale Semiconductor, Inc |
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MAC7200 Datasheet(HTML) 322 Page - Freescale Semiconductor, Inc |
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322 / 976 page ![]() Memory Map/Register Definition MAC7200 Microcontroller Family Reference Manual, Rev. 2 244 Freescale Semiconductor 13.2.1 Memory Map The Miscellaneous Control Module does not include any logic which provides access control. Rather, this function is supported using the standard access control logic provided by the IPS controller. Table 13-1. MCM 32-bit Memory Map MCM Offset Register 0x00 Processor Core Type (PCT) Revision (REV) 0x04 AXBS Master Configuration (AMC) AXBS Slave Configuration (ASC) 0x08 IPS Module Configuration (IMC) 0x0c Reserved Misc Reset Status (MRSR) 0x10 Reserved Misc Wakeup Control (MWCR) 0x14 Reserved Misc Software Watchdog Timer Control (MSWTCR) 0x18 Reserved Misc SWT Service (MSWTSR) 0x1c Reserved Misc Interrupt (MIR) 0x20 AXBS Address Map Register (AAMR) 0x24 Miscellaneous User-Defined Control Register (MUDCR) 0x28 Reserved NMI Control (NMICR) 0x28 Reserved 0x2c PPMRS PPMRC PPMRS1 PPMRC1 0x30 PPMRH[63:32] 0x34 PPMRL[31:0] 0x38 PPMR1H[63:32] 0x3c PPMR1L[31:0] 0x40 Reserved ECC Configuration (ECR) 0x44 Reserved ECC Status (ESR) 0x48 Reserved ECC Error Generation (EEGR) 0x4c Reserved 0x50 Flash ECC Address (FEAR) 0x54 Reserved Flash ECC Master (FEMR) Flash ECC Attributes (FEAT) 0x58 Reserved 0x5c Flash ECC Data (FEDR) 0x60 RAM ECC Address (REAR) 0x64 Reserved RAM ECC Syndrome (RESR) RAM ECC Master (REMR) RAM ECC Attributes (REAT) 0x68 Reserved 0x6c RAM ECC Data (REDR) 0x40 - 0x6c Reserved |
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