MAC7200 datasheet(323/976 Pages) FREESCALE

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Memory Map/Register Definition

MAC7200 Microcontroller Family Reference Manual, Rev. 2

Freescale Semiconductor

245

13.2.2

Attempted accesses to reserved addresses result in an error termination, while attempted writes to

read-only registers are ignored and do not terminate with an error. Unless noted otherwise, writes to the

programming model must match the size of the register, e.g., an n-bit register only supports n-bit writes,

etc. Attempted writes of a different size than the register width produce an error termination of the bus

cycle and no change to the targeted register.

13.2.2.1

Processor Core Type (PCT)

The PCT is a 16-bit read-only register specifying the architecture of the processor core in the device. The

state of this register is defined by a module input signal; it can only be read from the IPS programming

model. Any attempted write is ignored.

See Figure 13-1 and Table 13-2 for the Processor Core Type definition.

0x70 - 0x7c

Reserved

0x70

Core Fault Address (CFADR)

0x74

Reserved

Core Fault Location 1

(CFLOC1)

Core Fault Location

(CFLOC)

Core Fault Attributes

(CFATR)

0x78

Reserved

0x7c

Core Fault Data (CFDTR)

9876543210

PCT[15:0]

Reset

PCT[15:0]

Figure 13-1. Processor Core Type (PCT) Register

Table 13-2. PCT Field Descriptions

Field

Description

15–0

PCT[15:0

Processor Core Type. The device supports ARM, ColdFire and PowerPC cores. The following values

identify the specific core complexes:

A700

ARM7

A900

ARM9

A110

ARM11

CF20

V2 ColdFire

CF30

V3 ColdFire

CF40

V4 ColdFire

CF50

V5 ColdFire

E650

Z650 PowerPC

Table 13-1. MCM 32-bit Memory Map (Continued)

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