MAC7200 datasheet(327/976 Pages) FREESCALE

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Memory Map/Register Definition

MAC7200 Microcontroller Family Reference Manual, Rev. 2

Freescale Semiconductor

249

13.2.2.7

Miscellaneous Wakeup Control Register (MWCR)

Implementation of low-power sleep modes and exit from these modes via an interrupt require

communication between the MCM, the interrupt controller and external logic typically associated with

phase-locked loop clock generation circuitry. The Miscellaneous Wakeup Control Register (MWCR)

provides an 8-bit register controlling entry into these types of low-power modes as well as definition of

the interrupt level needed to exit the mode.

The following sequence of operations is generally needed to enable this functionality. Note that the exact

details are likely to be system-specific.

1. The processor core loads the appropriate data value into the MWCR, setting the ENBWCR bit and

the desired interrupt priority level.

2. At the appropriate time, the processor ceases execution. The exact mechanism varies by processor

core. In some cases, a processor-is-stopped status is signaled to the MCM and external logic. This

assertion, if properly enabled by MWCR[ENBWCR], causes the selected external, low-power

mode, as specified by MWCR[LPMD], to be entered, and the appropriate clock signals disabled.

In most implementations, there are multiple low-power modes, where the exact clocks to be

disabled vary across the different modes.

3. After entering the low-power mode, the interrupt controller enables a special combinational logic

path which evaluates all unmasked interrupt requests. The device remains in this mode until an

event which generates an unmasked interrupt request with a priority level greater than the value

programmed in the MWCR[PRILVL] occurs.

4. Once the appropriately-high interrupt request level arrives, the interrupt controller signals its

presence, and the MCM responds by asserting an “exit_low_power_mode” signal.

5. The external logic senses the assertion of the “exit” signal, and re-enables the appropriate clock

signals.

6. With the processor core clocks enabled, the core handles the pending interrupt request.

See Figure 13-7 and Table 13-8 for the Miscellaneous Wakeup Control Register definition.

SWTR

Software Watchdog Timer Reset.

1 Last recorded event was a reset caused by the MCM’s software watchdog timer.

4–0

Reserved, should be cleared.

765

43210

ENBWCR

LPMD[1:0]

PRILVL[3:0]

Reset

00000000

Figure 13-7. Miscellaneous Wakeup Control (MWCR) Register

Table 13-7. MRSR Field Descriptions (Continued)

Field

Description

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