MAC7200 datasheet(331/976 Pages) FREESCALE

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Memory Map/Register Definition

MAC7200 Microcontroller Family Reference Manual, Rev. 2

Freescale Semiconductor

253

out, writing to this register has no effect in negating the SWT interrupt or reset. Figure 13-9 illustrates the

MSWTSR.

If the software watchdog timer is enabled (MSWTCR[SWE] = 1), then any write of a data value other

than 0x55 or 0xAA generates an immediate system reset, regardless of the value in the MSWTCR[SWRI]

field.

13.2.2.10 Miscellaneous Interrupt Register (MIR)

All interrupt requests associated with MCM are collected in the MIR register. This includes the software

watchdog timer interrupt and the processor core system bus fault interrupt.

During the appropriate interrupt service routine handling these requests, the interrupt source contained in

the MCMIR must be explicitly cleared. See Figure 13-10 and Table 13-10.

765

43210

SWSR[7:0]

Reset

————————

Figure 13-9. Miscellaneous Software Watchdog Timer Service (MSWTSR) Register

765

43210

000000

CFEI

SWTIC

Reset

00000000

Figure 13-10. Miscellaneous Interrupt (MIR) Register

Table 13-10. MIR Field Descriptions

Field

Description

7–2

Reserved, should be cleeared.

CFEI

Code Fault Error Interrupt Flag.

0 An enabled processor core system bus fault has not occurred..

1 An enabled processor core system bus fault has occurred. The faulting address, attributes (and

possibly write data) are captured in the CFADR, CFATR, and CFDTR registers. The error interrupt is

only enabled if CFLOC[ECFEI] is set. The interrupt request is negated by writing a 1 to this bit. Writing

a 0 has no effect..

SWTIC

Software Watchdog Interrupt Flag.

0 An SWT interrupt has not occurred.

1 An SWT interrupt has occurred. The interrupt request is negated by writing a 1 to this bit. Writing a 0

has no effect.

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