MAC7200 datasheet(329/976 Pages) FREESCALE

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Memory Map/Register Definition

MAC7200 Microcontroller Family Reference Manual, Rev. 2

Freescale Semiconductor

251

the watchdog timer is serviced anytime in the first 75% of the time-out period, an immediate system reset

occurs.

Throughout Section 13.2.2.8, “Miscellaneous Software Watchdog Timer Control Register (MSWTCR),

there are numerous references to the generation of a system reset. MCM’s behavior during this process is

detailed below. When the watchdog timer expires and MSWTCR[SWRI] is programmed for a reset (either

as the initial or secondary response), the MCM generates a watchdog timer reset output signal which is

driven off the device where it is typically combined with other reset signals and driven throughout the

system. The combined reset input signal is driven back to the device and MCM, where MRSR[SWTR] can

be set and the appropriate action taken by the core and device logic.

The watchdog timer logic also sends an interrupt request to the device’s interrupt controller.

To prevent the watchdog timer from interrupting or resetting, the MSWTSR must be serviced by

performing the following sequence:

•

Write 0x55 to the MSWTSR.

•

Write 0xAA to the MSWTSR.

Both writes must occur in this order before the time-out, but any number of instructions can be executed

between the two writes. This definition allows interrupts and exceptions to occur, if necessary, between

the two writes. The timer value is constantly compared with the time-out period specified by

MSWTCR[SWT]. Any write to the MSWTCR resets the watchdog timer. In addition, there is a read-only

control flag included in the MSWTCR to prevent accidental updates to this control register from changing

the desired system configuration.

If the second write occurs at the exact same cycle as the time-out condition is reached, the clear takes

precedence and the time-out response suppressed.

The MSWTCR controls the software watchdog timer, time-out periods, and time-out response. The

Figure 13-8 and Table 13-9 for the Miscellaneous Software Watchdog Timer Control Register definition.

9876543210

00000

SWE

SWRI[1:0]

SWT[4:0]

Reset

0000000000000000

Figure 13-8. Miscellaneous Software Watchdog Timer Control (MSWTCR) Register

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