MAC7200 datasheet(328/976 Pages) FREESCALE

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Memory Map/Register Definition

MAC7200 Microcontroller Family Reference Manual, Rev. 2

250

Freescale Semiconductor

13.2.2.8

Miscellaneous Software Watchdog Timer Control Register (MSWTCR)

The software watchdog timer (SWT) prevents system lockup if the software becomes trapped in a loop

with no controlled exit or if a bus transaction becomes “hung.” The software watchdog timer can be

enabled or disabled through the MSWTCR[SWE]. By default, it is disabled. The SWT operates in a

separate, asynchronous clock domain and contains clock domain synchronizers as the communication

mechanism between the system clock domain and the software watchdog timer domain. If enabled, the

watchdog timer requires the periodic execution of a software watchdog servicing sequence. If this periodic

servicing action does not occur, the timer expires, resulting in a watchdog timer interrupt or a hardware

reset, as programmed in the MSWTCR[SWRI].

There are three user-defined responses to a time-out:

1. The MSWTCR[SWRI] can specify the assertion of a watchdog timer interrupt.

2. The MSWTCR[SWRI] can specify the immediate assertion of a system reset.

3. The MSWTCR[SWRI] can specify a sequence of responses. Upon the first time-out, a watchdog

timer interrupt is asserted. If this time-out condition is not serviced before a second time-out

occurs, the watchdog timer asserts the system reset signal in response to the second time-out. This

configuration supports a more graceful response to watchdog time-outs: first attempting an

interrupt to notify the system, and if that fails, generating a system reset.

In addition to these three basic modes of operation, the watchdog timer also supports a “windowed” mode

of operation. In this mode, the time-out period is divided into 4 equal segments and the actual servicing of

the watchdog timer must occur during the last segment, i.e., during the last 25% of the time-out period. If

Table 13-8. MWCR Field Descriptions

Field

Description

ENBWCR

Enable WCR.

0MWCR is disabled.

1 MWCR is enabled.

Reserved, should be cleared.

5–4

LPMD[1:0]

Low Power Mode. Used to select the low-power mode the chip enters once the ColdFire core executes

the STOP instruction. These bits must be written prior to instruction execution for them to take effect. The

LPMD bits are readable and writable in all modes.

0b00 Run

0b01 Doze

0b10 Wait

0b11 Stop

Note: If MWCR[LPMD] is cleared, then the device will stop executing code upon issue of a STOP

instruction. However, no clocks will be disabled.

3–0

PRILVL[3:0]

Interrupt Priority Level. The interrupt priority level is a core-specific definition. It specifies the interrupt

priority level needed to exit the low-power mode. Specifically, an unmasked interrupt request of a priority

level greater than the PRILVL value is required to exit the mode.

Certain interrupt controller implementations include logic associated with this priority level that restricts

the data value contained in this field to a [0, maximum - 1] range. See the specific interrupt controller

module for details.

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