MAC7200 datasheet(330/976 Pages) FREESCALE

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Memory Map/Register Definition

MAC7200 Microcontroller Family Reference Manual, Rev. 2

252

Freescale Semiconductor

13.2.2.9

Miscellaneous Software Watchdog Timer Service Register (MSWTSR)

The software service sequence must be performed using the MSWTSR as a data register to prevent a SWT

time-out. The service sequence requires two writes to this data register: first a write of 0x55 followed by

a write of 0xAA. Both writes must be performed in this order prior to the SWT time-out, but any number

of instructions or accesses to the SWSR may occur between the two writes. If the SWT has already timed

Table 13-9. MSWTCR Field Definitions

Field

Description

Read-Only.

0 MSWTCR can be read or written.

1 MSWTCR can only be read. A system reset is required before this register can again be written. The

setting of this bit is intended to prevent accidental writes of the MSWTCR from changing the defined

system watchdog configuration.

14–10

Reserved, should be cleared.

SWCIN16

Force SWT CarryIn16. This control bit is intended for use only when testing the operation of the SWT.

When asserted, it forces the actual timer to increment by 65537 (216 + 1) each cycle rather than simply

by 1. It allows testing of the large SWT time-out values without actually incrementing through the entire

dynamic range.

SWRWH

Software Watchdog Run While Halted.

0 SWT stops counting if the processor core is halted.

1 SWT continues to count even while the processor core is halted.

SWE

Software Watchdog Enable

0 SWT is disabled.

1 SWT is enabled.

6–5

SWRI[1:0]

Software Watchdog Reset/Interrupt.

00 If a time-out occurs, the SWT generates an interrupt to the processor core. The programming of the

interrupt level for the SWT is system-specific. Typically, the highest priority interrupt level is used to

signal the SWT.

01 The first time-out generates an interrupt to the processor, and if not serviced, then a second time-out

generates a system reset and sets the MRSR[SWTR] flag.

10 If a time-out occurs, the SWT generates a system reset. MRSR[SWTR] is set.

11 The SWT functions in a “window” mode of operation. For this mode, the servicing of the MSWSR must

occur during the last 25% of the time-out period. Any writes to the MSWSR during the first 75% of the

time-out period generate an immediate system reset. Likewise, if the MSWSR is not serviced during

the last 25% of the time-out period, then a system reset is generated. For any type of reset response,

the MRSR[SWTR] flag is set.

As noted previously, the generation of a system reset actually causes the MCM module to assert an

output signal which is driven out of the device where it is combined with other reset signals and then

driven throughout the system.

4–0

SWT[4:0]

Software Watchdog Time-Out Period. This field selects the time-out period for the SWT. At reset, this field

is cleared selecting the minimum time-out period, but the SWT is disabled since MSWTCR[SWE] = 0.

In general, the value in this field defines the bit position within the 32-bit counter that specifies the time-out

period. Thus, if SWT[4:0] = n, then the time-out period is 2n system clock cycles. Since it is not practical

to operate the software watchdog timer with very short time-out periods, data values of [0-7] are forced

to a value of 8, defining a minimum time-out period of 256 system clock cycles. The logic which forces the

minimum value to 8 does not affect the contents of this field in the register.

For SWT[4:0] = n, then time-out period = 2n system clock cycles, n = 8,9,..., 31.

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