MAC7200 datasheet(334/976 Pages) FREESCALE

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Memory Map/Register Definition

MAC7200 Microcontroller Family Reference Manual, Rev. 2

256

Freescale Semiconductor

13.2.2.13 NMI Control Register (NMICR)

The NMICR is an 8-bit register controlling the operation of a non-maskable interrupt. This functionality

is specifically provided to compensate for processor cores which do not directly support this type of

interrupt request. This logic operates by forcing error terminations (or aborts) on instruction fetches once

a properly-enabled NMI request is asserted. The resulting exception processing of the prefetch abort then

provides the required NMI service routine. The NMI input signal is treated as an edge-sensitive event, and

the request must be negated before a subsequent NMI is recognized. The required sequence of operations

is detailed below:

1. The NMICR is written to enable the non-maskable request and specify the polarity of the input

signal. The NMICR is a write-once register and any subsequent writes to this register are ignored.

2. Once an enabled NMI request is detected, the MCM logic begins forcing error terminations on all

instruction prefetches from the processor. At the same time, both FIQ and IRQ interrupt requests

are disabled by this logic.

3. The error tagging of instruction prefetches continues until the processor recognizes the prefetch

abort exception and accesses the exception vector at address 0x0000_000c.

4. Once the prefetch abort exception handler begins execution, the state of the NMICR[NMI_PEND]

flag is checked by the handler. If NMI_PEND = 1, then the prefetch abort was generated by a

pending NMI request, and execution continues in the appropriate NMI service routine.

5. Eventually, the source of the NMI request is negated. The service routine must properly adjust the

value of the CPSR to enable/disable FIQ and IRQ interrupts as required. The MCM logic disables

both the FIQ and IRQ inputs to the processor core while a properly-enabled NMI request is

asserted.

See Table 13-13 and Table 13-13 for the NMI Control Register definition.

65432

R NMI_PEND

0000

NMI_POL

NMI_ENB

Reset

—

——

Figure 13-13. NMI Control (NMICR) Register

Table 13-13. NMICR Field Descriptions

Field

Description

NMI_PEND

Non-Maskable Interrupt Pending.

0 Non-Maskable Interrupt is not pending

1 Non-Maskable Interrupt is pendin

6–2

Reserved, should be cleared.

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