MAC7200 datasheet(335/976 Pages) FREESCALE

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Memory Map/Register Definition

MAC7200 Microcontroller Family Reference Manual, Rev. 2

Freescale Semiconductor

257

Figure 13-14. Non-Maskable Interrupt Operation Timing

13.2.2.14 Peripheral Power Management Registers (PPMR)

The Miscellaneous Control Module implements two 64-bit IPS peripheral power management control

registers along with 4 additional registers for easy manipulation of these configuration registers.

13.2.2.14.1

Peripheral Power Management Set Register (PPMRS)

The PPMRS register provides a simple memory-mapped mechanism to set a given bit in the PPMR{H,L}

registers to disable the clock for a given IPS module without the need to perform a read-modify-write on

the PPMR. The data value on a register write causes the corresponding bit in the PPMR{H,L} register to

be set. A data value of 64 to 127 provides a global set function, forcing the entire contents of the

PPMR{H,L} to be set, disabling all IPS module clocks. Reads of this register return all zeroes. See

Figure 13-15 and Figure 13-14 for the PPMRS definition.

NMI_POL

Non-Maskable Interrupt Polarity.

0 Non-Maskable Interrupt is active low

1 Non-Maskable Interrupt is active high

NMI_ENB

Non-Maskable Interrupt Enable.

0 Non-Maskable Interrupt is disabled

1 Non-Maskable Interrupt is enabled

Table 13-13. NMICR Field Descriptions (Continued)

Field

Description

op1 if1 if2 if3 0xc

vec

idle

active_nmi

wf_nmi_negate

idle

clk

nmicr[nmi_enb]

nmicr[nmi_pol]

nmi_b

nmicr[nmi_pend]

fiq_b

irq_b

cpu_addr[*]

cpu_operand

cpu_data[*]

cpu_abort

nmi_fsm[*]

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