MAC7200 datasheet(339/976 Pages) FREESCALE

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Memory Map/Register Definition

MAC7200 Microcontroller Family Reference Manual, Rev. 2

Freescale Semiconductor

261

13.2.2.14.6

Peripheral Power Management Register 1 (PPMR1{H,L})

The PPMR1{H,L} registers provide a bit map for controlling the generation of the module clocks for each

decoded address space associated with the optional AIPS1 controller. Recall each AIPS controller decodes

the mapped address space into sixty-four 16 KByte “slots” (32 on-platform and 32 off-platform) and a 63

MByte off-platform global region. The PPMR1 provides a unique control bit for each of these address

spaces that defines whether the module clock for the given space is enabled or disabled. It is software’s

responsibility to appropriately disable module clocks using the PPMR1 only when a module is completely

unused or quiescent.

The individual bits of the PPMR1 can be modified using a read-modify-write to this register directly or

indirectly through writes to the PPMRS1 and PPMRC1 registers to set/clear individual bits. If the static

module enable is negated, the appropriate PPMR1 bit is automatically set by MCM after the negation of

the platform reset and cannot be altered by any subsequent IPS writes.

See Figure 13-21, Figure 13-22, and Figure 13-19 for the PPMR1 definition.

CD31 CD30 CD29 CD28 CD27 CD26 CD25 CD24 CD23 CD22

CD20 CD19 CD18 CD17

Reset

000000000000000

9876543210

CD15 CD14 CD13 CD12 CD11 CD10 CD09 CD08 CD07 CD06 CD05 CD04 CD03 CD02 CDG

Reset

000000000000000

Figure 13-20. Peripheral Power Management Register Low (PPMRL)

Table 13-18. Peripheral Power Management (PPMRH, PPMRL) Field Description

Field

Description

63–2

CD[63:2]

Clock Disable, Module Slot n.

0 The clock for this IPS module is enabled.

1 The clock for this IPS module is disabled.

CDG

0 The clock for the global IPS space is enabled.

1 The clock for the global IPS space is disabled.

Reserved, should be cleared.

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