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MAC7200 Datasheet(PDF) 342 Page - Freescale Semiconductor, Inc

Part # MAC7200
Description  MAC7200 Microcontroller Family Reference Manual
PDF  976 Pages
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MAC7200 Datasheet(HTML) 342 Page - Freescale Semiconductor, Inc

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Memory Map/Register Definition
MAC7200 Microcontroller Family Reference Manual, Rev. 2
264
Freescale Semiconductor
Register address: MCM Base + 0x43
765
43210
R0
0
ER1BR
EF1BR
00
ERNCR
EFNCR
W
Reset
00000000
Figure 13-23. ECC Configuration (ECR) Register
Table 13-20. ECR Field Descriptions
Field
Description
7–6
Reserved, should be cleared.
5
ER1BR
Enable RAM 1-bit Reporting.
0 Reporting of single-bit RAM corrections is disabled.
1 Reporting of single-bit RAM corrections is enabled.
This bit can only be set if the SoC-configurable input enable signal is asserted. The occurrence of a
single-bit RAM correction generates a MCM ECC interrupt request as signalled by the assertion of
ESR[R1BC]. The address, attributes and data are also captured in the REAR, RESR, REMR, REAT and
REDR registers.
4
EF1BR
Enable Flash 1-bit Reporting.
0 Reporting of single-bit flash corrections is disabled.
1 Reporting of single-bit flash corrections is enabled.
This bit can only be set if the SoC-configurable input enable signal is asserted. The occurrence of a
single-bit flash correction generates a MCM ECC interrupt request as signalled by the assertion of
ESR[F1BC]. The address, attributes and data are also captured in the FEAR, FEMR, FEAT and FEDR
registers.
3–2
Reserved, should be cleared.
1
ERNCR
Enable RAM Non-Correctable Reporting.
0 Reporting of non-correctable RAM errors is disabled.
1 Reporting of non-correctable RAM errors is enabled.
The occurrence of a non-correctable multi-bit RAM error generates a MCM ECC interrupt request as
signalled by the assertion of ESR[RNCE]. The faulting address, attributes and data are also captured in
the REAR, RESR, REMR, REAT and REDR registers.
0
EFNCR
Enable Flash Non-Correctable Reporting.
0 Reporting of non-correctable flash errors is disabled.
1 Reporting of non-correctable flash errors is enabled.
The occurrence of a non-correctable multi-bit flash error generates a MCM ECC interrupt request as
signalled by the assertion of ESR[FNCE]. The faulting address, attributes and data are also captured in
the FEAR, FEMR, FEAT and FEDR registers.



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