MAC7200 datasheet(346/976 Pages) FREESCALE

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Memory Map/Register Definition

MAC7200 Microcontroller Family Reference Manual, Rev. 2

268

Freescale Semiconductor

FR11BI

Force RAM One 1-bit Data Inversion.

0 No RAM single 1-bit data inversion is generated.

1 One 1-bit data inversion in the RAM is generated.

The assertion of this bit forces the RAM controller to create one 1-bit data inversion, as defined by the bit

position specified in ERRBIT[6:0], on the first write operation after this bit is set.

The normal ECC generation takes place in the RAM controller, but then the polarity of the bit position

defined by ERRBIT is inverted to introduce a 1-bit ECC event in the RAM.

After this bit has been enabled to generate a single 1-bit data inversion, it must be cleared before being

set again to properly re-enable the error generation logic.

This bit can only be set if the same SoC configurable input enable signal (as that used to enable single-bit

correction reporting) is asserted.

11–10

Reserved, should be cleared.

FRCNCI

Force RAM Continuous Non-correctable Data Inversions.

0 No RAM continuous 2-bit data inversions are generated.

1 2-bit data inversions in the RAM are continuously generated.

The assertion of this bit forces the RAM controller to create 2-bit data inversions, as defined by the bit

position specified in ERRBIT[6:0] and the overall odd parity bit, continuously on every write operation.

After this bit has been enabled to generate another continuous non-correctable data inversion, it must be

cleared before being set again to properly re-enable the error generation logic.

The normal ECC generation takes place in the RAM controller, but then the polarity of the bit position

defined by ERRBIT and the overall odd parity bit are inverted to introduce a 2-bit ECC error in the RAM.

FR1NCI

Force RAM One Non-correctable Data Inversions.

0 No RAM single 2-bit data inversions are generated.

1 One 2-bit data inversion in the RAM is generated.

The assertion of this bit forces the RAM controller to create one 2-bit data inversion, as defined by the bit

position specified in ERRBIT[6:0] and the overall odd parity bit, on the first write operation after this bit is

set.

The normal ECC generation takes place in the RAM controller, but then the polarity of the bit position

defined by ERRBIT and the overall odd parity bit are inverted to introduce a 2-bit ECC error in the RAM.

After this bit has been enabled to generate a single 2-bit error, it must be cleared before being set again

to properly re-enable the error generation logic.

Table 13-22. EEGR Field Descriptions (Continued)

Field

Description

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