MAC7200 datasheet(345/976 Pages) FREESCALE

345 / 976 page

Memory Map/Register Definition

MAC7200 Microcontroller Family Reference Manual, Rev. 2

Freescale Semiconductor

267

For both types of memories (RAM and flash), the intent is to generate errors during data write cycles, such

that subsequent reads of the corrupted address locations generate ECC events, either single-bit corrections

or double-bit non-correctable errors that are terminated with an error response.

The enabling of these error generation modes requires the same SoC-configurable input enable signal (as

that used to enable single-bit correction reporting) be asserted.

See Figure 13-25 and Table 13-22 for the ECC Configuration Register definition.

If an attempt to force a non-correctable inversion (by asserting EEGR[FRCNCI] or EEGR[FRC1NCI])

and EEGR[ERRBIT] equals 64, then no data inversion will be generated.

9876543210

ERRBIT[6:0]

Reset

000000000000000

Figure 13-25. ECC Error Generation (EEGR) Register

Table 13-22. EEGR Field Descriptions

Field

Description

15–14

Reserved, should be cleared.

FRC1BI

Force RAM Continuous 1-Bit Data Inversions.

0 No RAM continuous 1-bit data inversions are generated.

1 1-bit data inversions in the RAM are continuously generated.

The assertion of this bit forces the RAM controller to create 1-bit data inversions, as defined by the bit

position specified in ERRBIT[6:0], continuously on every write operation.

The normal ECC generation takes place in the RAM controller, but then the polarity of the bit position

defined by ERRBIT is inverted to introduce a 1-bit ECC event in the RAM.

After this bit has been enabled to generate another continuous 1-bit data inversion, it must be cleared

before being set again to properly re-enable the error generation logic.

This bit can only be set if the same SoC configurable input enable signal (as that used to enable single-bit

correction reporting) is asserted.

MAC7200 Datasheet(PDF) 345 Page - Freescale Semiconductor, Inc