MAC7200 datasheet(344/976 Pages) FREESCALE

344 / 976 page

Memory Map/Register Definition

MAC7200 Microcontroller Family Reference Manual, Rev. 2

266

Freescale Semiconductor

13.2.2.15.3

ECC Error Generation Register (EEGR)

The ECC Error Generation Register is a 16-bit control register used to force the generation of single- and

double-bit data inversions in the memories with ECC, most notably the RAM. This capability is provided

for two purposes:

•

It provides a software-controlled mechanism for “injecting” errors into the memories during data

writes to verify the integrity of the ECC logic.

•

It provides a mechanism to allow testing of the software service routines associated with memory

error logging.

It should be noted that while the EEGR is associated with the RAM, similar capabilities exist for the flash,

i.e., the ability to program the non-volatile memory with single- or double-bit errors is supported for the

same two reasons previously identified.

Table 13-21. ESR Field Descriptions

Field

Description

7–6

Reserved, should be cleared.

R1BC

RAM 1-bit Correction.

0 No reportable single-bit RAM correction has been detected.

1 A reportable single-bit RAM correction has been detected.

This bit can only be set if ECR[EPR1BR] is asserted. The occurrence of a properly-enabled single-bit

RAM correction generates a MCM ECC interrupt request. The address, attributes and data are also

captured in the REAR, RESR, REMR, REAT and REDR registers. To clear this interrupt flag, write a 1 to

this bit. Writing a 0 has no effect.

F1BC

Flash 1-bit Correction.

0 No reportable single-bit flash correction has been detected.

1 A reportable single-bit flash correction has been detected.

This bit can only be set if ECR[EPF1BR] is asserted. The occurrence of a properly-enabled single-bit

flash correction generates a MCM ECC interrupt request. The address, attributes and data are also

captured in the FEAR, FEMR, FEAT and FEDR registers. To clear this interrupt flag, write a 1 to this bit.

Writing a 0 has no effect.

3–2

Reserved, should be cleared.

RNCE

RAM Non-Correctable Error.

0 No reportable non-correctable RAM error has been detected.

1 = A reportable non-correctable RAM error has been detected.

The occurrence of a properly-enabled non-correctable RAM error generates a MCM ECC interrupt

request. The faulting address, attributes and data are also captured in the REAR, RESR, REMR, REAT

and REDR registers. To clear this interrupt flag, write a 1 to this bit. Writing a 0 has no effect.

FNCE

Flash Non-Correctable Error.

0 No reportable non-correctable flash error has been detected.

1 A reportable non-correctable flash error has been detected.

The occurrence of a properly-enabled non-correctable flash error generates a MCM ECC interrupt

request. The faulting address, attributes and data are also captured in the FEAR, FEMR, FEAT and FEDR

registers. To clear this interrupt flag, write a 1 to this bit. Writing a 0 has no effect.

MAC7200 Datasheet(PDF) 344 Page - Freescale Semiconductor, Inc

MAC7200 Datasheet(HTML) 344 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL